A common configuration of a conventional receiver in the direct conversion system will be shown in FIG. 1. An RF signal received through an antenna is supplied to an input terminal 1, and is then amplified by a low noise amplifier (Low Noise Amplifier; hereinafter referred to as an LNA) 2. Then, the amplified signal is branched into two paths. The branched signals are respectively down-converted by down-conversion mixers (hereinafter referred to as mixers) 3a and 3b on the respective paths. In this case, local signals (hereinafter referred to as LO signals) cos ωt and sin ωt having a phase difference of 90 degrees to each other, supplied from local signal input terminals 4a and 4b are selected so that a frequency of each of the LO signals cos ωt and sin ωt is the same as a carrier frequency of a desired RF signal. With this arrangement, a baseband signal is obtained by one time down-conversion.
Baseband signals output from the mixers 3a and 3b are respectively converted to digital signals through gain variable amplifiers 5a and 5b, 7a and 7b, low-pass filters (hereinafter referred to as LPFs) 6a and 6b for channel selection, and analog/digital converters (hereinafter referred to as ADCs) 8a and 8b. The digital signals obtained by the conversion are processed at a baseband signal processing unit (BB) 9.
A gain control unit (gain setting unit) 10 controls gains of results obtained by the processing in respective stages of the LNA2 and the gain variable amplifiers 5a, 5b, 7a, and 7b, if necessary, based on a time slot, bit error rate data, a reception strength, and the like of a received signal.
In the receiver in the direct conversion system described above, the baseband down-conversion is performed before components other than channel signals are filtered. Thus, in view of the presence of an interference wave, a sufficient gain cannot be obtained in a stage before the mixers 3a and 3b. Accordingly, the intensities of desired waves after the down-conversion are basically weak. A DC offset influence on each of the outputs of the mixers 3a and 3b is relatively large.
It is known that DC offsets are generated by some mechanisms other than a DC level drift of each of the outputs of the mixers 3a and 3b caused by variations in elements. Principal ones of the DC offsets will be shown in FIGS. 2 to 5.
FIG. 2 shows a DC offset generated by LO signal self mixing of an LO signal to be supplied through a local signal input terminal 4, which makes a detour to an RF port of a mixer 3 through a path 11 due to leakage or the like. This is a so-called static offset that does not vary with time.
FIG. 3 shows a DC offset generated by the LO signal to be supplied from the local signal input terminal 4. The LO signal passes through a path 12, and makes a detour to the RF port of the mixer 3 from the input terminal 1 of the LNA2, thereby generating the DC offset. An amount of the DC offset varies depending on gain setting of the LNA 2. Accordingly, at a time gain setting of the LNA2 immediately after reception, the amount of the DC offset varies. Further, the LO signal that has made a detour to the input terminal 1 of the LNA 2 may flow back to the antenna, and may be radiated into the space. Then, the LO signal may return to the LNA 2 and the mixer 3 through the antenna again. In this case, the DC offset is a dynamic offset that varies according to a change in an ambient environment.
FIG. 4 shows a DC offset caused by self mixing of an RF signal. The DC offset is generated by supply of a portion of the RF signal received through the antenna to the LO signal port 4 of the mixer 3 through a path 13. This DC offset noticeably occurs when there is a strong interference wave in a frequency band in the vicinity of the desired RF signal. The reception strength of the interference wave is varied by an influence such as fading. Thus, this DC offset is a dynamic offset.
FIG. 5 shows a DC offset generated by a portion of the RF signal amplified by the LNA 2. The portion of the RF signal makes a detour to the LO signal input terminal 4 of the mixer 3 through a path 14. The DC offset has both a dynamic DC offset property caused by the fading or the like and a property of a stepwise DC offset variation caused by a gain change in the LNA 2. In addition to the fading and the gain change in the LNA2, a second order distortion of the mixer 3 also varies the DC offset.
When the DC offset generated by one of the mechanisms described above is supplied to each of the gain variable amplifiers 7a and 7b, an amount of the DC offset is amplified. Generally, gain variable amplifiers perform amplification of several times to several thousand times. Thus, the amount of the DC offset is also amplified several times to several thousand times. In each of the gain variable amplifiers 7a and 7b, the amplified DC offset becomes a DC voltage bias level that has not been assumed at a time of designing. Then, the gain variable amplifiers 7a and 7b are brought into an inoperable state. Signal processing cannot be thereby performed.
Accordingly, a circuit for suppressing an increase in the DC offset is necessary for a receiver in the direct conversion system. As prior arts that suppress a DC offset in the receiver in this direct conversion system, Patent Documents 1 and 2 listed below are disclosed.
FIG. 6 shows a diagram illustrating a configuration of a gain control circuit described in Patent Document 1. This circuit has a configuration in which an output of a gain control amplifier 16 is fed back to a subtractor 19 on an input side through an amplifier 17 and an integrator 18, thereby reducing a DC gain. In this circuit, by controlling a gm (transconductance) value of the integrator 18 so that the DC gain becomes constant according to gain control of the gain control amplifier 16, a DC offset variation in a gain control circuit 20 at a time of gain control can be reduced.
FIG. 7 shows a diagram illustrating a configuration of a signal processing device described in Patent Document 2. An input signal to this circuit is supplied to a high-pass filter (hereinafter referred to as an HPF) 23 from a terminal 21. An output of the HPF 23 is branched into inputs to an output terminal 22 and an LPF 25. When a DC offset voltage of the output of the HPF 23 exceeds a voltage set by a determination element 26 in advance, a switch 28 is turned ON, thereby connecting an output node of the HPF 23 to the ground to discharge electric charges. When the electric charges are discharged, an output DC level of the HPF 23 is reduced, so that the DC offset voltage is suppressed. On the contrary, when the DC offset voltage falls below the voltage set by the determination element 26 in advance, a switch 27 is turned ON, thereby connecting the output node of the HPF 23 to a power supply to charge electric charges. When the electric charges are charged, the DC level is increased, so that the DC offset voltage is suppressed.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P-2001-156566A
[Patent Document 2]
International Publication No. WO2005/112282 pamphlet